PIC16F74T-E/L【PDF 74/104 页】IC MCU FLASH 4KX14 A/D 44PLCC

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Sheet目录3890

70页 71页 72页 73页 [74页]75页 76页 77页 78页

Micrel, Inc.

KSZ8851-16MLLJ

March 2010

M9999-030210-1.0

RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR

This register is used to program the received data byte count threshold.

Bit

Default Value

R/W

Description

15-0

0x0000

RXDBCT Receive Data Byte Count Threshold

To program received data byte threshold value in byte count.

When bit 6 set to 1 in RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13

in ISR) when the number of received bytes in RXQ buffer exceeds the threshold set in this

Interrupt Enable Register (0x90 – 0x91): IER

This register enables the interrupts from the QMU and other sources.

Bit

Default Value

R/W

Description

0x0

LCIE Link Change Interrupt Enable

When this bit is set, the link change interrupt is enabled.

When this bit is reset, the link change interrupt is disabled.

0x0

TXIE Transmit Interrupt Enable

When this bit is set, the transmit interrupt is enabled.

When this bit is reset, the transmit interrupt is disabled.

0x0

RXIE Receive Interrupt Enable

When this bit is set, the receive interrupt is enabled.

When this bit is reset, the receive interrupt is disabled.

0x0

Reserved

0x0

RXOIE Receive Overrun Interrupt Enable

When this bit is set, the Receive Overrun interrupt is enabled.

When this bit is reset, the Receive Overrun interrupt is disabled.

0x0

Reserved

0x0

TXPSIE Transmit Process Stopped Interrupt Enable

When this bit is set, the Transmit Process Stopped interrupt is enabled.

When this bit is reset, the Transmit Process Stopped interrupt is disabled.

0x0

RXPSIE Receive Process Stopped Interrupt Enable

When this bit is set, the Receive Process Stopped interrupt is enabled.

When this bit is reset, the Receive Process Stopped interrupt is disabled.

0x0

Reserved

0x0

TXSAIE Transmit Space Available Interrupt Enable

When this bit is set, the Transmit memory space available interrupt is enabled.

When this bit is reset, the Transmit memory space available interrupt is disabled.

0x0

RXWFDIE Receive Wake-up Frame Detect Interrupt Enable

When this bit is set, the Receive wakeup frame detect interrupt is enabled.

When this bit is reset, the Receive wakeup frame detect interrupt is disabled.

0x0

RXMPDIE Receive Magic Packet Detect Interrupt Enable

When this bit is set, the Receive magic packet detect interrupt is enabled.

When this bit is reset, the Receive magic packet detect interrupt is disabled.

0x0

LDIE Linkup Detect Interrupt Enable

When this bit is set, the wake-up from linkup detect interrupt is enabled.

When this bit is reset, the linkup detect interrupt is disabled.

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